The matrix-type display device has a scanning signal line driving circuit and a data signal line driving circuit, which often include a shift register for generating a scanning signal to be supplied to each scanning signal line, or for controlling of a timing at which a voltage is sampled from an image signal so as to apply the voltage to each data signal line.
Further, in recent years, a new display device capable of displaying a mirror image of the displayed image has come into practical use, which is often used for a monitor panel of a video camera or a digital camera. This kind of display device displays a mirror image by vertically or horizontally reversing the original image according to the angle of the image display section. Such a display device capable of reversing a displayed image uses a bidirectional shift register as the shift register. The bidirectional shift register is capable of changing the shifting direction, and therefore allows the display device to carry out such a mirror image display by only switching the shifting direction without storing the image signal.
Meanwhile, power consumption of an electronic circuit increases in proportion to the frequency, the load capacitance, and the square of the voltage. Therefore, in a periphery circuit, connected to the display device, such as a circuit for generating an image signal supplied to the display device, or in the display device itself, the driving voltage is becoming lower and lower in order to reduce power consumption.
However, for a display device in which a driving circuit (such as a scanning signal line driving circuit and/or a data signal line driving circuit) is monolithically formed in a single substrate as well as a pixel circuit, in order to obtain a wider display area, especially for the display device including the scanning signal line driving circuit and/or the data signal line driving circuit made of polycrystalline silicon thin film transistors; the difference of the threshold voltages between the respective substrates or even within a single substrate may become almost as large as several voltages. In this case, the reduction of driving voltage cannot be successfully realized.
Accordingly, the scanning signal line driving circuit and/or the data signal line driving circuit supplied with a signal from a circuit, such as the foregoing circuit for generating an image signal, which is made of monocrystal silicon transistors and is driven by a voltage of 3.3V, 5V, or lower voltage, receives an input signal lower than that of the driving voltage of the shift register, and therefore a level shifter for increasing the input voltage is required.
One specific example is explained by referring to a scanning direction control circuit 1 shown in FIG. 21, which shows a bidirectional shift register 2 (hereinafter simply referred to as a shift register 2) constituted of 6 flip-flops f1 through f6 and 12 analog switches a1 through a6 and b1 through b6. When a clock signal CK with an amplitude of approximately 5V, a starting signal SP, and a shifting direction switching signal L/R are supplied to the bidirectional shift register 2, level shifters 3 through 5 respectively steps up the voltages of those signals, for example, to 15V, which is the driving voltage of the shift register 2.
In response to (a) the switching signal L/R whose voltage has been stepped up by the level shifter 5, and (b) a signal generated by inverting the switching signal L/R by an inverter circuit 6, the analog switches al through a6 and b1 through b6 for switching input of the flip-flops f1 through f6 carry out antithetical operations, so that the direction for shifting the starting signal SP in synchronism with the clock signal CK is changed to f1, f2, . . . , f6 or to f6, f5, . . . f1.
FIGS. 22 and 23 are electric circuit diagrams showing specific examples of a general level shifter. The level shifter shown in FIG. 22 includes NMOS transistors qn1 and qn2, PMOS transistors qp1 through qp4, and an inverter circuit inv.
Further, the PMOS transistors qp1 and qp2 and the NMOS transistor qn1 are provided in series between a high level VDD power source line and a ground level power source line. Similarly, the PMOS transistors qp3 and qp4 and the NMOS transistor qn2 are provided in series between those two power source lines. An input signal IN is supplied to the gate terminals of the PMOS transistor qp2 and the NMOS transistor qn1, and an inversion signal of the input signal IN is created by the inverter circuit inv and supplied to the gate terminals of the PMOS transistor qp4 and the NMOS transistor qn2. The drain terminals of the PMOS transistor qp2 and the NMOS transistor qn1 are connected to the gate terminal of the PMOS transistor qp3, and the drain terminals of the PMOS transistor qp4 and the NMOS transistor qn2 are connected to the gate terminal of the PMOS transistor qp1, and also to be an output terminal from which an output signal OUT is outputted.
In such an arrangement, when the input signal IN becomes high level, the NMOS transistor qn1 is turned on and the PMOS transistor qp3 is turned on, and then the PMOS transistor qp4 is turned on, the NMOS transistor qn2 is turned off, and the PMOS transistor qp1 is turned off, and the output signal OUT becomes high level (VDD). In this manner, the output signal OUT with a voltage which has been stepped up to VDD is outputted in the same phase as the input signal IN which has a low amplitude.
To operate the level shifter of FIG. 22, the voltage level of the input signal IN is required to be greater to a certain extent than the threshold voltages for the respective NMOS transistors qn1 and qn2. When the voltage level of the input voltage IN becomes lower than or close to the threshold values for the NMOS transistors qn1 and qn2, it may cause a problem, such as malfunction of the level shifter, or an exceptional increase of delay time of the output signal OUT.
However, one of the transistors is turned off in the series circuit of the PMOS transistor qp1 and the NMOS transistor qn2, and in the series circuit of the PMOS transistor qp3 and the NMOS transistor qn4, and therefore, a steady-state current does not flow in the level shifter section. Thus, it is possible to realize a system structure with low power consumption.
Meanwhile, the level shifter of FIG. 23 includes NMOS transistors qn11 through qn14 and PMOS transistors qp11 through qp14. Further, the PMOS transistor qp11 whose gate terminal is connected to ground, and the NMOS transistor qn11 connected to function as a diode are provided in series between the high level VDD power source line and the ground level power source line. Further, the PMOS transistor qp12 whose gate terminal is connected to ground, and the NMOS transistor qn12 constituting a current mirror circuit with the NMOS transistor qn11 are provided in series between the high level VDD power source line and the input terminal.
The output signal of the drain terminal of the PMOS transistor qp12 and the NMOS transistor qn12 is inverted by a CMOS inverter constituted of the PMOS transistor qp13 and the NMOS transistor qn13, and is further inverted and outputted by a CMOS inverter constituted of the PMOS transistor qp14 and the NMOS transistor qn14.
In this arrangement, a steady-state current always flows in the PMOS transistor qp11 and the NMOS transistor qn11, and the steady-state current further flows into the PMOS transistor qp12 and the NMOS transistor qn12. As a result, a predetermined gate voltage is generated, and the PMOS transistor qp11 and the NMOS transistor qn11 come into operation.
A voltage between gate and source of the NMOS transistor qn12 changes depending on the input signal IN so as to change the gate voltage of the PMOS transistor qp13 and the NMOS transistor qn13. This causes the CMOS inverter made of the PMOS transistor qp13 and the NMOS transistor qn13, and the CMOS inverter made of the PMOS transistor qp14 and the NMOS transistor qn14 to come into operation so as to carry out level shifting of the input signal IN which has a low amplitude. The signal which has been subjected to the level shifting is then outputted as an output signal OUT.
The level shifter of FIG. 23 may be brought into operation even when the voltage level of the input signal IN is not greater to a certain extent than that of the threshold voltage of the transistor. This level shifter however causes an increase of power consumption since the steady-state current always flows in the level shifter section.
Generally, a circuit made of monocrystal silicon transistors, because of having relatively small threshold values, uses the level shifter of FIG. 22, and a circuit made of a polycrystalline silicon thin film transistor, because of having relatively large threshold values, uses the level shifter of FIG. 23.
As described, when a polycrystalline silicon thin film transistor is used for the scanning direction control circuit 1 of FIG. 21, which is used as the scanning signal line driving circuit or the data signal line driving circuit, the scanning direction control circuit adopts the level shifter of FIG. 23. The level shifter of FIG. 23 may be adopted with no particular problems for a signal showing a frequent change, such as the clock signal CLK or the shift starting signal SP, because such a signal causes dominant power consumption due to the circuit operation, apart from the steady-state current. In contrast, this power consumption affects a signal which changes a shifting direction, which seldom changes, of the bidirectional shift register 2.
Further, when the shifting direction is changed in the bidirectional shift register 2, it is necessary to change the switching signal after the previous shifting operation by the bidirectional shift register 2 is completed but before a new starting signal SP is supplied to the shift register 2. This is because of the following reason. Namely, if the switching signal is changed during the signal shifting by the shift register 2, there arises an over current somewhere in the flip-flops f1 through f6, due to a short-circuit between input and output, which may cause malfunction of the shifting operation.
Further, when the shift register 2 is mounted in a display device, the foregoing problem may occur in the scanning signal line driving circuit, for example, when the switching signal is changed during the shifting operation by the shift register. Besides, such a change of the switching signal changes the scanning direction in the halfway of one screen display, and therefore, image display cannot be properly performed in some periods.
In view of the foregoing problems, in order to supply the switching signal at predetermined timings, it is necessary to arrange a new logic for securely inputting the signal after the previous shifting operation by the bidirectional shift register is completed but before the starting signal is newly supplied, regardless the timing of change of the switching signal.